Complex integrated circuits, for example memory devices, programmable logic devices, etc., often include on-chip testing features which allow a designer (or customer) to verify operation of the integrated circuit prior to shipping (or use). To use these test mode features, the integrated circuit, or at least a portion of the functional circuitry which makes up the integrated circuit, must be placed in a test mode. In other words, the test mode must be activated.
In the past, test modes for integrated circuits have been activated in one of three ways. In some cases, test modes are entered by the application of "over-voltages" or "super-voltages" to one or more pins of the integrated circuit. In other cases, special test mode control pins are provided to allow activation of the test mode. In still further schemes, test modes may be entered through a unique addressing sequence applied to the integrated circuit.
Each of the above three schemes for entering a test mode presents potential hazards. With super-voltages, one always runs the risk of damaging sensitive circuitry contained on the integrated circuit. While the use of extra or special test mode activation pins avoids this problem, it requires that additional space be provided for the test mode control pins and may present compatibility problems. Address sequencing, although it avoids the problems of super-voltages and extra pins, presents a potential risk in as much as the user may inadvertently key the address sequence for entering the test mode without meaning to do so. Therefore, what is required is a method and apparatus for entering test mode of an integrated circuit which reduces the risk of unintentionally triggering the test mode and avoids the other problems presented by schemes of the past.